Generally, the implementation of a phase-locked loop (PLL) requires the acquisition of an appropriate frequency and phase using an internal ring oscillator. Analog phase-locked loops typically use a voltage-controlled oscillator (VCO) to generate a period signal that is "locked" to a reference clock signal. The frequency of the VCO is modulated by an analog voltage adjusted via a feedback mechanism. Typically, the feedback mechanism is supplied from a sequential phase/frequency detector. The sequential phase/frequency detector outputs an "up" or "down" pulse proportional to phase error width and in the direction required to pull in the frequency of the VCO output signal to the target reference clock signal. The output of a sequential phase/frequency detector usually enables a charge pump driving a loop filter (RC), which in turn controls the frequency of the VCO. The detector outputs can be arbitrarily small, and thus there is usually a dead band associated with such a detector where, for a certain window of time, there is no detectable output. Accordingly, during the dead band ("window width"), the PLL can detect neither "up" nor "down" pulses for a phase/frequency error of a magnitude equal to or less than the window width. This technique has been used in many applications, and requires careful tuning to maintain the right damping characteristics.
In the PLL, the gain of the VCO is defined as dF/dV (the change in VCO frequency per change in the analog control voltage). The maximum change in frequency occurs when there is a maximum amount of phase error during a given cycle (maximum dV). The change in analog control voltage (dV), depends on many parameters, such as, the charge pump, loop filter, etc. Consequently, the loop gain of the PLL requires careful tuning of these parameters to maintain the right damping characteristics. If the gain is too high, the PLL will be unstable, resulting in excessive jitter or loss of lock. Conversely, if the gain is too low, the PLL may not be able to track frequency drift due to fluctuations in the reference frequency, V.sub.DD, or temperature. Thus, the gain (dF/dV) must be constrained, which causes the PLL to suffer unnecessary time penalties during phase and frequency acquisition.
Once a PLL has acquired phase-lock, a mechanism must be provided such that the operating point of the PLL can move due to changes in temperature, voltage or reference clock frequency. For example, as a microprocessor heats up, the oscillator will slow down. To maintain the correct frequency/phase relationship, the controlling logic must compensate in a way to speed up the oscillator frequency. Similarly, increases or decreases in supply voltage require the frequency to change. In systems, it is not unusual for the reference clock to change frequencies, either to optimize power/performance, or to minimize electro-magnetic interference effects.